Senior RTL Verification Engineer — FPGA/ASIC
Fortaegis Technologies
Role description
Fortaegis Technologies in Amsterdam is seeking a Design Verification Engineer to verify RTL designs for FPGA and ASIC-based products, ensuring alignment with system-level requirements.
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The role emphasizes owning verification strategies, building environments, and close collaboration with design and software teams to deliver robust, high-performance hardware solutions.
You will implement xgiwjmb coverage-driven verification, stay current with industry practices, and contribute to ultra-secure products in
